MIM capacitor integrated into the damascene structure and method of making thereof

ABSTRACT

This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.

TECHNICAL FIELD

This invention relates generally to semiconductor device fabrication andmore particularly to the integration of metal-insulator-metal (MIM)capacitors with the damascene interconnect structure and process.

BACKGROUND

Capacitors are critical components of analog integrated circuit devicesand memory devices. They are also used in many mixed signal or highfrequency applications requiring both high performance and high speed.Low series resistance, low loss, high Q and low (RC) time constants arerequired in these high frequency applications for high performance.Metal-insulator-metal (MIM) capacitors are commonly used, such as inhigh performance applications.

MIM capacitors typically include metal electrodes separated by adielectric. The MIM structure and materials frequently andadvantageously allow integration of its fabrication with the damasceneinterconnect process. In conventional methods, the electrodes are madefrom Al, Cu, or alloys thereof. The thin insulating dielectric layer isusually made from silicon oxide or silicon nitride deposited by chemicalvapor deposition (CVD). MIM capacitors offer a number of advantagesproviding a relatively constant value of capacitance over a relativelywide range of voltages. Conventional MIM capacitors have a relativelysmall parasitic resistance, however, they also have a number ofdisadvantages.

Advanced technology applications frequently require a capacitance inexcess of 100 nF. Even with an ultra thin gate oxide, high capacitancerequires a large silicon area, thereby increasing die size as well aschip and assembly cost. Ultra thin oxides also lead to unacceptably highleakage currents in integrated circuits (e.g. 100 mA for 0.1 mm² of 12 Ågate oxide). These factors cause problems with power and thermalmanagement, they shorten battery life for mobile applications, and theyincrease overall cost.

Current MIM capacitor manufacturing methods require a number ofphotolithographic steps to form electrodes and dielectric layers. Sincethe cross-sectional area of the capacitor plug is small and thedifference in height between damascene and capacitor plugs may be great,etching is very difficult to control. If the capacitor metal electrodelayers and its dielectric layer are formed on an entire layer duringfabrication, production costs are very high. When etching to form theelectrodes and dielectric layer, it is very easy to cause damage on theedge portion of the metal capacitor.

The following references provide additional background. In U.S. Pat. No.6,680,542, Gibson et al. show a metal-on-metal capacitor structure andprocess and an associated damascene process. In U.S. Pat. No. 6,358,792,Hsue et al. show a method for fabricating a lower capacitor electrodeconcurrently with an interconnect metal. In U.S. Pat. No. 6,140,693,Weng et al. show a metal capacitor for ultra large-scale integration(ULSI) compatible with the damascene process. In U.S. Pat. No.6,069,051, Nguyen et al. show a method of fabricating metal-to-metalcapacitors using planar processing compatible with the damasceneprocess. In U.S. Pat. No. 6,492,226, Hsue et al. show a method forforming a metal capacitor in a damascene process. In U.S. Pat. No.6,559,493, Lee et al. show an improved stacked MIM capacitor. In U.S.Pat. No. 6,436,787, Shih et al. show a method for forming a crown MIMcapacitor integrated with the damascene process. In U.S. Pat. Pub. No.2004/0201057, Lien et al. show a method for forming a MIM capacitor in acopper damascene process. However, none of these references describesthe novel structure and method of this invention that provides for theintegration of specific elements of a MIM capacitor into a damascenefabrication process.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention that provide a method and structure for thecreation of a metal-insulator-metal (MIM) capacitor. By using adamascene barrier liner for capacitor plates and an etch stop layer as acapacitor dielectric, fabrication costs are reduced without sacrificingcapacitor density or performance.

An embodiment of the invention provides a semiconductor device. Apreferred device comprises an interconnect structure such as damascenestructure having a conductive via formed through a first interleveldielectric layer and a first dielectric etch stop layer located underthe first interlevel dielectric layer. Preferably, the conductive viacontacts a first interconnect structure located under the firstdielectric etch stop layer. The structure may further comprise aconductive trench formed through a second interlevel dielectric layerand a second dielectric etch stop layer located between the first andsecond interlevel dielectric layers. In preferred embodiments, theconductive trench contacts the conductive via.

Further components of the preferred device comprise a first plateelectrode formed on a second interconnect structure located under thefirst dielectric etch stop layer and a second plate electrode formed onthe first dielectric etch stop layer and substantially overlapping thefirst plate electrode. Embodiments further include a second damasceneinterconnect structure formed through the first and second interleveldielectric layers and the first dielectric etch stop layer andcontacting the second plate electrode. Embodiments of the inventionadvantageously provide a MIM capacitor integrated with a damasceneinterconnect structure.

In other embodiments of the invention, a MIM capacitor comprises a firstelectrode formed on a second interconnect structure, wherein the secondinterconnect structure is located under a dielectric etch stop layer.Embodiments further comprise a second electrode formed on the dielectricetch stop layer. Preferably, the second plate electrode is substantiallyparallel to the first plate electrode and substantially overlapping thefirst plate electrode. Preferred embodiments further include a secondinterlevel conductive via formed through the interlevel dielectric layerand contacting the second electrode.

Still other embodiments of the invention provide a method of fabricatinga MIM capacitor. The method comprises providing a substrate having afirst conductive interconnect structure and a second conductiveinterconnect structure and depositing a first layer of diffusion barriermaterial over the substrate. The first layer of diffusion barriermaterial is patterned to form a first capacitor electrode over thesecond interconnect structure. Preferred embodiments further includeforming a first dielectric etch stop layer over the substrate and overthe first capacitor electrode. A second layer of diffusion barriermaterial is formed over the first dielectric etch stop layer, and it ispatterned to form a second capacitor electrode located substantiallydirectly above the first capacitor electrode. A first interleveldielectric layer is formed over the first dielectric etch stop layer andover the second capacitor electrode. A second dielectric etch stop layeris formed over the first interlevel dielectric layer, and a secondinterlevel dielectric layer is formed over the second dielectric etchstop layer. Preferred embodiments may further comprise forming a firstdamascene interconnect structure through the first and second interleveldielectric layers, the second dielectric etch stop layer, and contactingthe second capacitor electrode. Preferred embodiments may also furthercomprise forming a second damascene interconnect structure through thefirst and second interlevel dielectric layers, the first and seconddielectric etch stop layers and contacting the first conductiveinterconnect structure.

The diffusion barrier and liner materials may comprise TiN, W, Al, Alalloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys,TaN, TiN, Ti, Ta, Ra, Ru, or combinations thereof. Preferably, firstcapacitor electrode and the second capacitor electrode have a maximumdimension greater than or equal to a maximum lateral damascene trenchdimension.

Embodiments of this invention advantageously provide for a flexiblefabrication process that supports a wide range of applicationrequirements. Embodiments further provide for on-circuit decouplingcapacitor applications, since the embodiments' processing requirementsare less stringent than precision analog requirements. Fabrication ofpreferred embodiments require only one additional mask to form thecapacitor plates, and it even this step is simplified because thedimensional requirements of the capacitor plates are far less stringentthan other device features.

The foregoing has outlined rather broadly the features and technicaladvantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter, which form the subject of the claims of the invention. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiment disclosed may be readily utilized as a basis formodifying or designing other structures or processes for carrying outthe same purposes of the present invention. It should also be realizedby those skilled in the art that such equivalent constructions do notdepart from the spirit and scope of the invention as set forth in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1A to 1D are cross-sectional views of an embodiment of the presentinvention illustrating an intermediate semiconductor device and theformation of the bottom capacitor electrode;

FIG. 2 is a cross-sectional view of an embodiment of the presentinvention further including MIM damascene capacitor electrodes and anESL;

FIG. 3 is a cross sectional view of an embodiment of the presentinvention further including damascene capacitor electrodes and damasceneinterconnect openings;

FIG. 4 is a cross sectional view of an embodiment of the presentinvention illustrating a completed MIM capacitor integrated into thedamascene interconnect structure; and

FIG. 5 is a cross sectional view of an embodiment of the presentinvention illustrating an exemplary DRAM that includes a completed MIMcapacitor integrated into the damascene interconnect structure.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention. Thepresent invention will be described with respect to preferredembodiments in a specific context, namely a copper damasceneinterconnect process.

Turning now to FIGS. 1A through 1D, these figures are cross-sectionalviews of an embodiment of the present invention illustrating anintermediate semiconductor device and the formation of the first orbottom capacitor electrode as described below. FIG. 1A depicts a crosssectional view of an integrated circuit at an intermediate fabricationstage. Shown in FIG. 1A is a conventional substrate 101, which comprisesas a silicon wafer or a silicon on insulator (SOI) structure on which isformed a dielectric such as an interlevel dielectric (ILD), anintermetallic dielectric (IMD), or other dielectric. Substrate 101includes a first trench opening 103 and a second trench opening 105. Thetrenches may be formed using conventional photolithographic patterningand anisotropic etching methods.

Referring to FIG. 1A, a barrier layer 107 is conformably, blanketdeposited to line at least the trench openings 103 and 105 and at leasta portion of the surface of substrate 101 that is adjacent the trenchopening. The barrier layer is preferably about 10 to 30 Angstroms thick,and it forms a barrier for Cu diffusion. The barrier layer 107 mayinclude TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co,Al, AlCu alloy, W, Ti, Ta, Ra, Ru, combinations thereof, and alloysthereof. In alternative embodiments the barrier layer 107 is a metalrich nitride, either throughout the bulk or only on the surface.

In alternative embodiments, barrier layer 107 includes a first barrierlayer on the surface of the substrate and a second barrier layer on thefirst barrier layer. The first barrier layer includes an atomic layerdeposited (ALD) material such as Ta, W, and combinations thereof. Thesecond barrier layer may comprise the same material as the first barrierlayer.

The barrier layer 107 may be applied using physical vapor deposition(PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), or plasma enhanced atomic layer deposition (PEALD),atomic layer deposition (ALD), or other conventional techniques.

After depositing barrier layer 107, interconnect structures are formedby filling trench openings 103 and 105 with a conductor 109, as shown inFIG. 1B. In other embodiments, a glue layer (not shown) may beinterposed between the barrier layer 107 and an overlying conductor 109.The optional glue layer enhances adhesion between adjacent layers. Itmay be about 10 to 500 Angstroms thick, preferably less than about 150Å. It may be applied using PVD, CVD, PECVD, PEALD, and, preferably, ALDat about 100-300° C. It may consist essentially of Ru, Ta, Ti, W, Co,Ni, Nb, Al, AlCu alloy, and combinations thereof.

An optional Cu seed layer (not shown) may be deposited on the barrierlayer 107. Prior to deposition of conductor 109, a seed layer isoptionally deposited over the glue layer or barrier layer by, forexample, PVD and/or CVD. The seed layer, preferably copper, is PVDdeposited to form a continuous layer about 400 to 700 Å thick over thewafer process surface, thereby providing a continuously conductivesurface for depositing the bulk of the copper during the ECD process.

Still referring to FIG. 1B, a conductor 109, preferably copper, iselectroplated according to a conventional electro-chemical deposition(ECD) process to fill trenches 103 and 105. Although other copperfilling methods such as PVD and CVD methods may be used, electroplating(electrodeposition) is preferred because of its superior gap-filling andstep coverage. Alternative embodiments may include a conductor 109consisting of Cu, Al, Au, or Ag, and combinations thereof, or alloyedcompositions thereof.

A chemical mechanical polishing (CMP) step may remove conductoroverfill, thereby resulting in the planar structure illustrated in FIG.1C. Following planarization, a portion of the diffusion barrier layer107 lines the sidewalls of the first 103 and second 105 trenches to forma trench liner 111. The trench liner 111 prevents outward diffusion ofthe conductor 107 into the surrounding substrate 101.

Turning now to FIG. 1D, a patterned layer of conductive material isformed over one of the trenches to form a first capacitor electrode 115.As shown in FIG. 1D, the first capacitor electrode 115 preferably coversthe conductor 109, the trench diffusion barrier liner 111, and anadjacent portion of the substrate 101. The first capacitor electrode 115is preferably about 10 to 1500 Å thick and more preferably about 10 to30 Å thick. It is fabricated using a metal such as TiN, W, Al, Alalloys, or any material that comprises a suitable diffusion barriermaterial. In preferred embodiments, the trench diffusion barrier liner111 and the first capacitor electrode 115 comprise the same material.

Next, a first dielectric etch stop layer (ESL) 117 is formed over thesubstrate 101 including the first capacitor electrode 115, asillustrated in this Figure. Etch stop layer 117 may include, forexample, silicon nitride, silicon carbide, and/or silicon oxynitride. Inaddition to etch control, it also preferably prevents Cu penetrationinto overlying layers. The ESL is preferably about 500 Å to 1500 Åthick, and it may be applied using PECVD. Preferred embodimentsadvantageously permit capacitance adjustment by varying the thicknessand/or area of electrode 115 and/or ESL 117.

Turning to FIG. 2, after the step of forming ESL 117, the second (ortop) capacitor electrode 200 is formed. The second capacitor electrode200 preferably includes the same material as the first electrode 115,and its formation may comprise essentially the same deposition andpatterning process described above. In preferred embodiments the topelectrode 115 is deposited using the same mask as bottom electrode 115.As illustrated in FIG. 2, the two capacitor electrodes are preferablyessentially parallel and overlapping, that is second electrode 200 issubstantially directly above the first electrode 115.

After forming the second capacitor electrode, 200, there is formed afirst interlevel dielectric layer 201, a second dielectric etch stoplayer 203 and a second interlevel dielectric layer 205. The dielectricetch stop layers 117 and 203, may comprise silicon nitride, siliconcarbide, combinations thereof, or any other similar etch stop material.The layers 117, 201, 203, and 205 may be formed by conventionaldeposition processes in a previous step, not shown. Two openings 207have also been conventionally formed within and through the secondinterlevel dielectric layer 205.

The interlevel dielectrics, 201 and 205, may independently comprisesilicon dioxide or any other dielectric material known for use in asemiconductor device. Advanced applications frequently employ low-k(i.e. k less than about 4) dielectrics. Suitable low-k dielectricsinclude, carbon doped silicon dioxide, also referred to as organosilicate glass (OSG) and C-oxide, borophosphosilicate glass (BPSG),borosilicate glass (BSG), phosphosilicate glass (PSG), fluorinatedsilicate glass (FSG), and porous oxides. Exemplary organic low-kmaterials include polyarylene ether, hydrogen silesquioxane (HSQ),methyl silsesquioxane (MSQ), polysilsequioxane, polyimide,benzocyclbbutene, and amorphous Teflon.

Turning to FIG. 3, there is illustrated the intermediate semiconductordevice illustrated in FIG. 2, after forming two damascene openings 210and 216. In accordance with preferred embodiments, the capacitordamascene trench 212 is formed through dielectric 205 and down to ESL203. The capacitor via 214 is formed through ESL 203, through interleveldielectric 201, and down to capacitor electrode 200.

Continuing with FIG. 3, the contact damascene trench 218, is initiallyformed through dielectric layer 205 down to ESL 203. The contactdamascene via 220 is initially formed through ESL 203 and dielectric 201down to ESL 117.

The intermediate device is then processed further to form the completeddamascene opening 216 illustrated in FIG. 3. The capacitor damasceneopening 210 is protected with photoresist, and the contact damascenetrench 218 is then etched further. Contact via 220 is etched through ESL117, down to conductor material 109 in substrate 101. At the same time,contact trench 218 is etched through ESL 203 down to dielectric 201. Thephotomask is then removed, thereby producing the completed damasceneopenings 210 and 216.

Turning to FIG. 4, there is illustrated the intermediate device of FIG.3 after the processing described above and further including forming thecompleted damascene interconnect structures 310 and 316 according to apreferred embodiment of the invention.

Diffusion barrier layer 301 is preferably deposited within damasceneopenings 210 and 216 (of FIG. 3) according to the same proceduredescribed above with respect to barrier layers 200 and 111. Continuingwith FIG. 4, damascene openings are filled with conductor 309. Conductor309 is preferably copper and is deposited according to the processdescribed above with respect to conductor 109. After CMP planarizingmethods described above, the final damascene interconnect structures 310and 316 shown in FIG. 4 result. As described above, ECD copper mayfurther include a glue and/or a seed layer (not shown).

Referring now to FIG. 5, there is illustrated an exemplary semiconductordevice that incorporates embodiments described herein. Althoughembodiments of this invention have many applications, they are believedparticularly useful in a DRAM capacitor structure as illustrated in thecross sectional view of FIG. 5.

The method of fabricating a DRAM capacitor structure, featuring a MIMcapacitor integrated into the damascene structure, will now be describedin detail. Semiconductor substrate 401, comprised of P type, singecrystalline silicon, featuring a <100> crystallographic orientation, isused and schematically shown in FIG. 5. Silicon dioxide gate insulatorlayer 402, is thermally grown to a thickness between about 15 to 100Angstroms, followed by the formation of silicon nitride capped, polycidegate structure 405. Polycide layer 403, is comprised of an overlyingmetal silicide layer such as tungsten silicide, and an underlying, insitu doped, polysilicon layer 403. The underlying polysilicon layer isobtained via low pressure chemical vapor deposition (LPCVD), procedures,at a thickness between about 200 to 2000 Angstroms, and doped duringdeposition via the addition of arsine or phosphine, to a silane ambient.The overlying tungsten silicide layer is also obtained via LPCVDprocedures, at a thickness between about 200 to 2000 Angstroms, usingsilane and tungsten hexafluoride as reactants. Silicon nitride layer404, is then deposited at a thickness between about 100 to 1000Angstroms, via LPCVD or plasma enhanced chemical vapor deposition(PECVD) procedures. A photoresist shape, not shown in the drawings, isused as an mask to allow an anisotropic, reactive ion etching (RIE)procedure, using Cl₂ as an etchant, to define silicon nitride capped,polycide gate structure 405, shown schematically in FIG. 5. The width ofsilicon nitride capped, polycide gate structure 405, is between about100 to 1000 Angstroms.

After removal of the photoresist shape used for definition of thesilicon nitride capped, polycide gate structure, via plasma oxygenashing procedures, insulator spacers 406, on formed on the sides ofsilicon nitride capped, polycide gate structure 405. This isaccomplished via deposition of a silicon nitride, or a silicon oxidelayer, via LPCVD or PECVD procedures, at a thickness between about 100to 1500 Angstroms. An anisotropic RIE procedure, using CF₄ as an etchantis next used to form silicon nitride, or silicon oxide spacers on thesides of silicon nitride capped, polycide gate structure 405. Arsenic orphosphorous ions are next implanted into a region of semiconductorsubstrate 401, not covered by silicon nitride capped, polycide gatestructure 405, or by insulator spacers 406, at an energy between about 2to 100 KeV, at a dose between about 2E13 to 7E14 atoms/cm². An annealprocedure is next performed using either conventional furnace or rapidthermal anneal procedures, to activate the implanted ions, forming Ntype source/drain region 407, shown schematically in FIG. 5. Althoughthis invention is described for a N channel device, it can also beapplied to a channel device.

A dielectric layer 408, such as silicon oxide, boro-phosphosilicateglass (BPSG), or other IMD or ILD material, is next deposited at athickness between about 3000 to 12000 Angstroms, via LPCVD or PECVDprocedures. Planarization of dielectric layer 408, is then accomplishedvia a chemical mechanical polishing (CMP) procedure, resulting in asmooth top surface topography for dielectric layer 408.Photolithographic and anisotropic RIE procedures, using CHF₃ as anetchant, are used to define trench openings 420, and 421 withindielectric layer 408, so the trench openings now expose a top portion ofsource/drain regions 407. After removal of the photoresist shape used todefine openings 420, and 421, a trench barrier liner 451 is formed.

Following forming liner 451, a conductor, preferably copper, isdeposited using LPCVD procedures, at a thickness between about 3000 to12000 Angstroms, thereby completely filling trench openings 420, and421. Regions of unwanted copper located on the top surface of dielectriclayer 408 may be using CMP, thereby defining lower copper storage nodeplug structure 410, in opening 421, and copper bit line plug structure409, located in opening 420.

In accordance with preferred embodiments describe above, the firstelectrode 115 is formed by deposited a barrier layer material that issubsequently patterned as shown in FIG. 5. First electrode 115 ispreferably the same liner material 451 used to line openings 420 and421. The integrated MIM damascene capacitor fabrication is nextcompleted as described above. In accordance with preferred embodiments,damascene liners 460 and 461, trench liners 450 and 451, the firstcapacitor electrode 115, and the second capacitor electrode 200 allcomprise barrier material.

By way of further example, and as illustrated in FIG. 5, the lateraldimension of the damascene electrodes d is larger than the FET 405 gatewidth. In fact, as shown in FIG. 5, the capacitor electrode size d islarger than the via portion of the damascene interconnect structure 310.The lateral dimension d is limited by device density, but it ispreferably at least as wide as the maximum damascene opening, typicallythe trench.

The capacitor electrode geometry parameter d illustrates an advantagethat embodiments have over certain conventional damascene capacitors.Capacitor electrodes 115 and 200 are not constrained by the lateralgeometry of their attached conductive interconnects. For example, in aconventional damascene capacitor, the capacitor structure may consistonly of damascene interconnect 310, substrate interconnect 420, anddielectric 117. The addition of capacitor electrodes 115 and 200according to embodiments described herein, enable a flexibility inintegrated circuit design not possible with conventional methods andstructures. The ability to adjust the electrode geometry parameter dindependently of interconnect geometry permits a wider range ofcapacitance values than that achievable with conventional damascenecapacitors.

While the previous example illustrated a damascene MIM capacitor linkedwith a DRAM, embodiments are easily linked with other devices at anyother level, including the silicon substrate. Several other advantagesare summarized below.

Preferred embodiments are economically manufactured because the MIMelectrode fabrication process requires only one additional,photolithography process to form the capacitor plates. Furthermore,since the electrode dimensions are relatively much larger compared to aFET, the photolithography process is simple and straightforward.Embodiments also advantageously rely on etch selectivity between theplate material and ESL thereby eliminating the conventional etchingrequired to contact the capacitor top plate. Embodiments also eliminatethe high leakage levels associated with high capacitance, dense Sicapacitors having an ultra thin gate oxide. Embodiments easily providefor adjustment of capacitance density by varying the lower platethickness during deposition. For decoupling applications, capacitorformation is expected to have a sufficiently wide process window totranslate into increased production yield.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Theembodiments of the invention described above are exemplary and notlimiting, and variations that are apparent to those skilled in the artthat include the features of the invention are within the scope of theinvention and the appended claims.

1. A semiconductor device, comprising: a first damascene interconnectstructure comprising: a conductive via formed through a first interleveldielectric layer and a first dielectric etch stop layer located underthe first interlevel dielectric layer, wherein the conductive viacontacts a first interconnect structure located under the firstdielectric etch stop layer; a conductive trench formed through a secondinterlevel dielectric layer and a second dielectric etch stop layerlocated between the first and second interlevel dielectric layers,wherein the conductive trench contacts the conductive via; and ametal-insulator-metal capacitor comprising: a first plate electrodeformed on a second interconnect structure located under the firstdielectric etch stop layer; a second plate electrode formed on the firstdielectric etch stop layer and substantially overlapping the first plateelectrode; a second damascene interconnect structure formed through thefirst and second interlevel dielectric layers and the first dielectricetch stop layer and contacting the second plate electrode.
 2. Thesemiconductor device of claim 1, wherein the first and second plateelectrodes comprise a diffusion barrier.
 3. The semiconductor device ofclaim 2, wherein the diffusion barrier comprises a material selectedfrom the group consisting essentially of TiN, W, Al, Al alloys, TbN, VN,ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta,Ra, Ru, and combinations thereof.
 4. The semiconductor device of claim1, wherein the first interlevel dielectric layer and the secondinterlevel dielectric layer comprise a material selected from the groupconsisting essentially of silicon oxide, silicon nitride, siliconcarbide, organo silicate glass (OSG), borophosphosilicate glass (BPSG),borosilicate glass (BSG), phosphosilicate glass (PSG), fluorinatedsilicate glass (FSG), a porous oxides, polyarylene ether, hydrogensilesquioxane (HSQ), methyl silsesquioxane (MSQ), polysilsequioxane,polyimide, benzocyclbbutene, and combinations thereof.
 5. Thesemiconductor device of claim 1, wherein the first and second damasceneinterconnect structures are dual damascene interconnect structures. 6.The semiconductor device of claim 1 further comprising: a barrier linerbetween the first damascene interconnect structures and the first andsecond interlevel dielectric layers.
 7. The semiconductor device ofclaim 6, wherein the barrier liner comprises a material selected fromthe group consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN,CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra,Ru, and combinations thereof.
 8. The integrated capacitor of claim 1,wherein the first capacitor electrode and the second capacitor electrodehave a maximum dimension greater than or equal to a maximum lateraldamascene trench dimension.
 9. A semiconductor device, comprising: afirst interlevel conductive via formed through an interlevel dielectriclayer and a dielectric etch stop layer located under the interleveldielectric layer and contacting a first interconnect structure locatedunder the dielectric etch stop layer; and a metal-insulator-metalcapacitor comprising: a first electrode formed on a second interconnectstructure, the second interconnect structure located under thedielectric etch stop layer; a second electrode formed on the dielectricetch stop layer, the second plate electrode being substantially parallelto the first plate electrode and substantially overlapping the firstplate electrode; a second interlevel conductive via formed through theinterlevel dielectric layer and contacting the second electrode.
 10. Thesemiconductor device of claim 9, wherein the first and second electrodescomprise a diffusion barrier.
 11. The semiconductor device of claim 10,wherein the diffusion barrier comprises a material selected from thegroup consisting essentially of TiN, W, Al, Al alloys, TbN, VN, ZrN,CrN, WC, WN, WCN, NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra,Ru, and combinations thereof.
 12. The semiconductor device of claim 9,wherein the first and second interlevel conductive vias further includea barrier liner.
 13. The semiconductor device of claim 12, wherein thebarrier liner comprises a material selected from the group consistingessentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN,NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, andcombinations thereof.
 14. The integrated capacitor of claim 9, whereinthe first capacitor electrode and the second capacitor electrode have amaximum dimension greater than or equal to a maximum lateral secondinterlevel conductive via dimension.
 15. The semiconductor device ofclaim 9, wherein the first interlevel dielectric layer and the secondinterlevel dielectric layer comprise a material selected from the groupconsisting essentially of silicon oxide, silicon nitride, siliconcarbide, organo silicate glass (OSG), borophosphosilicate glass (BPSG),borosilicate glass (BSG), phosphosilicate glass (PSG), fluorinatedsilicate glass (FSG), a porous oxides, polyarylene ether, hydrogensilesquioxane (HSQ), methyl silsesquioxane (MSQ), polysilsequioxane,polyimide, benzocyclbbutene, and combinations thereof.
 16. A method offabricating a damascene metal-insulator-metal capacitor, the methodcomprising: providing a substrate, the substrate including a firstconductive interconnect structure and a second conductive interconnectstructure; depositing a first layer of diffusion barrier material overthe substrate; patterning the first layer of diffusion barrier materialto form a first capacitor electrode over the second interconnectstructure; forming a first dielectric etch stop layer over the substrateand over the first capacitor electrode; forming a second layer ofdiffusion barrier material over the first dielectric etch stop layer;patterning the second layer of diffusion barrier material to form asecond capacitor electrode located substantially directly above thefirst capacitor electrode; forming a first interlevel dielectric layerover the first dielectric etch stop layer and over the second capacitorelectrode; forming a second dielectric etch stop layer over the firstinterlevel dielectric layer; forming a second interlevel dielectriclayer over the second dielectric etch stop layer; forming a firstdamascene interconnect structure through the first and second interleveldielectric layers, the second dielectric etch stop layer, and contactingthe second capacitor electrode; and forming a second damasceneinterconnect structure through the first and second interleveldielectric layers, the first and second dielectric etch stop layers andcontacting the first conductive interconnect structure.
 17. Thesemiconductor device of claim 16, wherein the first layer of diffusionbarrier material and the second layer of diffusion barrier materialcomprise a material selected from the group consisting essentially ofTiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, Ni, Co,AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, and combinations thereof.
 18. Thesemiconductor device of claim 16, wherein forming the first and seconddamascene interconnect structures further includes a depositing barrierliner.
 19. The semiconductor device of claim 18, wherein the barrierliner comprises a material selected from the group consistingessentially of TiN, W, Al, Al alloys, TbN, VN, ZrN, CrN, WC, WN, WCN,NbN, AlN, Ni, Co, AlCu alloys, TaN, TiN, Ti, Ta, Ra, Ru, andcombinations thereof.
 20. The integrated capacitor of claim 16, whereinthe first capacitor electrode and the second capacitor electrode have amaximum dimension greater than or equal to a maximum lateral damascenetrench dimension.